Project Specifications

• Instruction Set Architecture

Status: Complete (version 2.0)
Validation Suite: Complete
Documentation: Complete

• Assembler

Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): Complete
Status: Fully operational and in regular service
Validation Suite: Complete
Documentation: Complete

• Linker

Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): To be done
Status: Fully operational and in regular service
Validation Suite: Complete
Documentation: Complete

• Emulator

Implemented in C
Integrated source-level debugging; multi-core support
Status: Fully operational and in regular service
Documentation: Complete

• KPL: Kernel Programming Language

Compiler #1 (implemented in C++): Complete
Compiler #2 (implemented in KPL): Complete
Validation Suite: Complete
Both compilers are fully functional
Status: Fully operational and in regular service
Documentation: Complete

• KPL Code Body

Assembler (~14,000 LOC)
KPL Compiler (~54,000 LOC)
Library Functions (~15,000 LOC)
Compiler Validation and Test Suite (~56,000 LOC)
Misc Demo Programs:
CacheSimulator, RelayComputerSimulator, LineEditor, etc.

• Blitz OS

Status: Design is in gestation

• Hardware

FPGA Implementation #1 (System Verilog)
    Status: Prototype, discontinued work
FPGA Implementation #2 (System Verilog)
    Implements full ISA (version 1.0)
    Passes validation suite
FPGA Implementation #3 (System Verilog)
    ISA version 2.0
    Work in progress
Single Board Computer: Planned