Project Specifications

• Processor Core

Instruction Set Architecture
    Design status: Complete
    Documentation: Complete
    Validation suite: Alpha version
FPGA Implementation #1 (System Verilog)
    Status: Prototype, discontinued work
FPGA Implementation #2 (System Verilog)
    Implements caches, full ISA
    Passes validation suite

• KPL: Kernel Programming Language

Compiler #1 (implemented in C++): Complete
Compiler #2 (implemented in KPL): Complete
Validation Suite: Complete
Both compilers are fully functional
KPL is fully operational and in regular service
Development: Complete
Documentation: Complete

• KPL Code Body

KPL Library Functions (~15,000 LOC)
Blitz Assembler (~14,000 LOC)
KPL Compiler (~54,000 LOC)
Compiler Validation and Test Suite (~56,000 LOC)
Major categories: Parsing, Semantics, Execution
Misc demo programs: CacheSimulator,
RelayComputerSimulator, LineEditor, etc

• Assembler

Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): Complete
Validation Suite: Both assemblers are fully operational
The assembler is fully operational and in regular service
Documentation: Complete

• Linker

Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): To be done
The linker is fully operational and in regular service
Documentation: Complete

• Emulator

Implemented in C
Fully operational and in regular service
Integrated source-level debugging
Multi-core support

• Blitz OS

Expected: December 2021

• Hardware

System Verilog FPGA Core: In Development
Single Board Computer: Planned