Status: Complete (version 2.1)
Validation Suite: Complete
Documentation: Complete
Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): Complete
Status: Fully operational and in regular service
Validation Suite: Complete
Both assemblers are fully functional and behave identically
Documentation: Complete
Version #1 (implemented in C): Complete
Version #2 (implemented in KPL): To be done
Status: Fully operational and in regular service
Validation Suite: Complete
Documentation: Complete
Implemented in C
Integrated source-level debugging; multi-core support
Status: Fully operational and in regular service
Documentation: Complete
Compiler #1 (implemented in C++): Complete
Compiler #2 (implemented in KPL): Complete
Validation Suite: Complete
Both compilers are fully functional and behave identically
Status: Fully operational and in regular service
Documentation: Complete
Assembler (~14,000 LOC)
KPL Compiler (~54,000 LOC)
Library Functions (~15,000 LOC)
Compiler Validation and Test Suite (~56,000 LOC)
xv6 Kernel (~17,000 LOC)
Misc Demo Programs:
CacheSimulator, RelayComputerSimulator, LineEditor, etc.
xv6 (Basic Unix Kernel)
Multicore operation
User mode programs (sh, cat, wc, grep, ...)
Status:
Completed
Test and validation suite passed
MicroBlitz Implementation
Coded in System Verilog (original work, no external IP)
Target:
Intel Quartus Prime software (Lite version)
Terasic “Cyclone V GX Starter Kit” development board
FPGA: Altera Cyclone V GX
Status:
Implements Full ISA (version 2.1)
Passes ISA Validation Suite
Executes Programs in Assembler and KPL
Future Work:
Platform Level Interrupt Controller (PLIC)
LLDR3 Memory Interface
Cache
Additional Peripheral Interfaces
Dedicated Single Board Computer
Documentation